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| a FEATURES ULTRALOW NOISE PERFORMANCE 2.9 nV/ Hz at 10 kHz 0.38 V p-p, 0.1 Hz to 10 Hz 6.9 fA/ Hz Current Noise at 1 kHz EXCELLENT AC PERFORMANCE 12.5 V/ s Slew Rate 20 MHz Gain Bandwidth Product THD = 0.0002% @ 1 kHz Internally Compensated for Gains of +5 (or -4) or Greater EXCELLENT DC PERFORMANCE 0.5 mV max Offset Voltage 250 pA max Input Bias Current 2000 V/mV min Open Loop Gain Available in Tape and Reel in Accordance with EIA-481A Standard APPLICATIONS Sonar Photodiode and IR Detector Amplifiers Accelerometers Low Noise Preamplifiers High Performance Audio PRODUCT DESCRIPTION Ultralow Noise, High Speed, BiFET Op Amp AD745 CONNECTION DIAGRAMS 8-Pin Plastic Mini-DIP (N) & 8-Pin Cerdip (Q) Packages OFFSET NULL 1 - IN 2 +IN 3 -VS 4 8 NC 16-Pin SOIC (R) Package NC 1 OFFSET NULL - IN 2 3 16 NC AD745 15 NC 14 NC 13 +VS 12 OUTPUT 11 OFFSET NULL AD745 TOP VIEW 7 +VS 6 OUTPUT 5 OFFSET NULL NC 4 +IN 5 -VS 6 NC = NO CONNECT NC 7 TOP VIEW 10 NC 9 NC NC 8 The AD745's guaranteed, tested maximum input voltage noise of 4 nV/Hz at 10 kHz is unsurpassed for a FET-input monolithic op amp, as is its maximum 1.0 V p-p noise in a 0.1 Hz to 10 Hz bandwidth. The AD745 also has excellent dc performance with 250 pA maximum input bias current and 0.5 mV maximum offset voltage. The internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. This makes the AD745 especially useful as a preamplifier where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. The AD745 is available in five performance grades. The AD745J and AD745K are rated over the commercial temperature range of 0C to +70C. The AD745A and AD745B are rated over the industrial temperature range of -40C to +85C. The AD745S is rated over the military temperature range of -55C to +125C and is available processed to MIL-STD-883B, Rev. C. The AD745 is available in 8-pin plastic mini-DIP, 8-pin cerdip, 16-pin SOIC, or in chip form. The AD745 is an ultralow noise, high speed, FET input operational amplifier. It offers both the ultralow voltage noise and high speed generally associated with bipolar input op amps and the very low input currents of FET input devices. Its 20 MHz bandwidth and 12.5 V/s slew rate makes the AD745 an ideal amplifier for high speed applications demanding low noise and high dc precision. Furthermore, the AD745 does not exhibit an output phase reversal. 1000 R SOURCE EO INPUT NOISE VOLTAGE - nV/ Hz OP37 & RESISTOR (--) 120 100 120 100 80 60 GAIN 40 20 0 -20 10M 100M R SOURCE 100 80 60 40 20 0 AD745 & RESISTOR OR OP37 & RESISTOR 10 AD745 + RESISTOR ( ) RESISTOR NOISE ONLY (- - -) 1 100 1k 10k 100k 1M 10M REV. C SOURCE RESISTANCE - -20 100 1k Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 10k 100k 1M FREQUENCY - Hz One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 PHASE MARGIN - Degrees OPEN-LOOP GAIN - dB PHASE AD745-SPECIFICATIONS Model Conditions INPUT OFFSET VOLTAGE Initial Offset Initial Offset vs. Temp. vs. Supply (PSRR) vs. Supply (PSRR) INPUT BIAS CURRENT 3 Either Input Either Input @ TMAX Either Input Either Input, V S = 5 V INPUT OFFSET CURRENT Offset Current @ TMAX FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion4 INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Max Operating Range 6 Common-Mode Rejection Ratio 1 (@ +25 C and 15 V dc, unless otherwise noted) Min AD745J/A Typ Max Units 0.25 TMIN to TMAX TMIN to TMAX 12 V to 18 V 2 TMIN to TMAX VCM = 0 V VCM = 0 V VCM = +10 V VCM = 0 V VCM = 0 V VCM = 0 V G = -4 VO = 20 V p-p G = -4 f = 1 kHz G = -4 20 120 12.5 5 0.0002 1 x 1010 20 3 x 1011 18 20 +13.3, -10.7 -10 VCM = 10 V TMIN to TMAX 0.1 to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz VO = 10 V RLOAD 2 k TMIN to TMAX RLOAD = 600 RLOAD 600 RLOAD 600 TMIN to TMAX RLOAD 2 k Short Circuit 80 78 95 2 96 1.0/0.8 1.5 90 88 mV mV V/C dB dB 150 400 8.8/25.6 600 200 150 2.2/6.4 pA nA pA pA pA nA 250 30 40 MHz kHz V/s s % pF pF V V V dB dB V p-p nV/Hz nV/Hz nV/Hz nV/Hz fA/Hz +12 INPUT VOLTAGE NOISE 0.38 5.5 3.6 3.2 2.9 6.9 5.0 4.0 INPUT CURRENT NOISE OPEN LOOP GAIN 1000 800 4000 1200 V/mV V/mV V/mV OUTPUT CHARACTERISTICS Voltage +13, -12 +13.6, -12.6 +12, -10 12 20 +13.8, -13.1 40 15 8 V V V V mA Current POWER SUPPLY Rated Performance Operating Range Quiescent Current TRANSISTOR COUNT 4.8 18 10.0 V V mA # of Transistors 50 NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes of operations at T A = +25C. 2 Test conditions: +V S = 15 V, -VS = 12 V to 18 V and +VS = 12 V to +18 V, -VS = 15 V. 3 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25C. For higher temperature, the current doubles every 10C. 4 Gain = -4, R L = 2 k, CL = 10 pF. 5 Defined as voltagc between inputs, such that neither exceeds 10 V from common. 6 The AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. All min and max specifications are guaranteed. Specifications subject to change without notice. -2- REV. C AD745 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range (Q) . . . . . . . . . -65C to +150C Storage Temperature Range (N, R) . . . . . . . -65C to +125C Operating Temperature Range AD745J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C AD745A/B . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD745S . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Pin Plastic Package: JA = 100C/W, JC = 50C/W 8-Pin Cerdip Package: JA = 110C/W, JC = 30C/W 8-Pin Plastic SOIC Package: JA = 100C/W, JC = 30C/W ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY An ESD classification per method 3015.6 of MIL-STD-883C has been performed on the AD745, which is a class 1 device. Using an IMCS 5000 automated ESD tester, the two null pins will pass at voltages up to 1000 volts, while all other pins will pass at voltages exceeding 2500 volts. ORDERING GUIDE Model AD745JN AD745AN AD745JR-16 Temperature Range 0C to +70C -40C to +85C 0C to +70C Package Option* N-8 N-8 R-16 *N = Plastic DIP; R = Small Outline IC. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). REV. C -3- AD745 -Typical Characteristics 20 (@ + 25 C, VS = 20 15 V unless otherwise noted) 35 INPUT VOLTAGE SWING - Volts R LOAD = 10k 15 +VIN OUTPUT VOLTAGE SWING - Volts RLOAD = 10k 15 POSITIVE SUPPLY OUTPUT VOLTAGE SWING - Volts p-p 30 25 20 15 10 5 0 10 10 -VIN 5 10 NEGATIVE SUPPLY 5 0 0 10 15 5 SUPPLY VOLTAGE + VOLTS - 20 0 0 5 10 15 SUPPLY VOLTAGE + VOLTS - 20 100 1k LOAD RESISTANCE - 10k Figure 1. Input Voltage Swing vs. Supply Voltage Figure 2. Output Voltage Swing vs. Supply Voltage Figure 3. Output Voltage Swing vs. Load Resistance 12 INPUT BIAS CURRENT - Amps 10 -6 10 -7 200 100 QUIESCENT CURRENT - mA 9 OUTPUT IMPEDANCE - 10 -8 10 -9 10 -10 10 6 1 CLOSED-LOOP GAIN = -5 0.1 3 10 -11 10 -12 -60 -40 -20 0 0 15 SUPPLY VOLTAGE VOLTS 5 10 20 0 20 40 60 80 100 120 140 TEMPERATURE - C 0.01 10k 100k 1M 10M FREQUENCY - Hz 100M Figure 4. Quiescent Current vs. Supply Voltage Figure 5. Input Bias Current vs. Temperature Figure 6. Output Impedance vs. Frequency 300 80 70 28 GAIN BANDWIDTH PRODUCT - MHz 26 24 22 20 18 16 14 -60 -40 -20 INPUT BIAS CURRENT - pA CURRENT LIMIT - mA 60 50 40 30 20 10 - OUTPUT CURRENT + OUTPUT CURRENT 200 100 0 -12 -9 -6 -3 3 6 9 0 COMMON-MODE VOLTAGE - Volts 12 0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 TEMPERATURE - C 0 20 40 60 80 100 120 140 TEMPERATURE - C Figure 7. Input Bias Current vs. Common-Mode Voltage Figure 8. Short Circuit Current Limit vs. Temperature Figure 9. Gain Bandwidth Product vs. Temperature -4- REV. C Typical Characteristics- AD745 120 100 120 100 14 150 RL = 2k PHASE MARGIN - Degrees OPEN-LOOP GAIN - dB 80 60 GAIN 40 20 0 80 60 40 20 0 -20 10M 100M SLEW RATE - Volts/s 12 OPEN-LOOP GAIN - dB PHASE 140 130 CLOSED-LOOP GAIN = +5 10 120 100 -20 100 8 -60 -40 -20 0 20 40 60 80 100 120 140 1k 10k 100k 1M FREQUENCY - Hz 80 0 TEMPERATURE - C 10 15 5 SUPPLY VOLTAGE VOLTS 20 Figure 10. Open-Loop Gain and Phase vs. Frequency 120 COMMON-MODE REJECTION - dB Figure 11. Slew Rate vs. Temperature 120 POWER SUPPLY REJECTION - dB Figure 12. Open-Loop Gain vs. Supply Voltage 35 30 25 R L = 2k 20 15 10 5 0 110 100 90 80 Vcm = 10V 70 60 50 100 + SUPPLY 80 60 40 - SUPPLY 20 1k 10k 100k 1M 10M FREQUENCY - Hz 0 100 OUTPUT VOLTAGE - Volts p-p 100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M FREQUENCY - Hz FREQUENCY - Hz Figure 13. Common-Mode Rejection vs. Frequency Figure 14. Power Supply Rejection vs. Frequency CURRENT NOISE SPECTRAL DENSITY - fA/ Hz Figure 15. Large Signal Frequency Response TOTAL HARMONIC DISTORTION (THD) - dB TOTAL HARMONIC DISTORTION (THD) - % Hz -40 1.0 100 1k -60 0.1 NOISE VOLTAGE (reffered to input) - nV/ -80 GAIN = +10 -100 GAIN = +100 -120 GAIN = -4 -140 10 0.01 10 CLOSED-LOOP GAIN = +5 100 0.001 10 1.0 0.0001 100 1k 10k 0.00001 100k 0.1 10 100 1k 10k 100k 1M 10M FREQUENCY - Hz 1.0 1 10 100 1k FREQUENCY - Hz 10k 100k FREQUENCY - Hz Figure 16. Total Harmonic Distortion vs. Frequency Figure 17. Input Noise Voltage Spectral Density Figure 18. Input Noise Current Spectral Density REV. C -5- AD745 -Typical Characteristics 72 66 60 54 TOTAL UNITS = 760 648 594 540 NUMBER OF UNITS +VS 1F + 0.1F NUMBER OF UNITS 486 432 378 324 270 216 162 108 54 48 42 36 30 24 18 12 6 0 -15 -10 -5 0 5 10 15 o INPUT OFFSET VOLTAGE DRIFT - V/ C TOTAL UNITS = 4100 2 7 AD745 5 1 3 0.1F 1F 4 6 VOS ADJUST 2M 1M + -V S 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 INPUT VOLTAGE NOISE @ 10kHz - nV/ Hz Figure 19. Distribution of Offset Voltage Drift. TA = +25C to +125C +VS VIN 0.1F 7 VOUT Figure 20. Typical Input Noise Voltage Distribution @ 10 kHz Figure 21. Offset Null Configuration, 8-Pin Package Pinout 3 2s 100 90 500nS 100 90 AD745 SQUARE WAVE INPUT 2 4 6 CL 10pF 0.1F -V S 2k 20pF 499 10 0 % 10 0 % 5V 50mV Figure 22a. Gain of 5 Follower, 8-Pin Package Pinout Figure 22b. Gain of 5 Follower Large Signal Pulse Response Figure 22c. Gain of 5 Follower Small Signal Pulse Response 20pF 2k 2s +VS 499 VIN 2 7 0.1 F VOUT 6 CL 0.1F 10pF 10 0 % 100 90 500nS 100 90 AD745 3 SQUARE WAVE INPUT 4 -V S 10 0 % 5V 50mV Figure 23a. Gain of 4 Inverter, 8-Pin Package Pinout Figure 23b. Gain of 4 Inverter Large Signal Pulse Response Figure 23c. Gain of 4 Inverter Small Signal Pulse Response -6- REV. C AD745 OP AMP PERFORMANCE JFET VS. BIPOLAR DESIGNING CIRCUITS FOR LOW NOISE The AD745 offers the low input voltage noise of an industry standard bipolar op amp without its inherent input current errors. This is demonstrated in Figure 24, which compares input voltage noise vs. input source resistance of the OP37 and the AD745 op amps. From this figure, it is clear that at high source impedance the low current noise of the AD745 also provides lower total noise. It is also important to note that with the AD745 this noise reduction extends all the way down to low source impedances. The lower dc current errors of the AD745 also reduce errors due to offset and drift at high source impedances (Figure 25). The internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. This makes the AD745 especially useful as a preamplifier, where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. 1000 R SOURCE EO R SOURCE AD745 & RESISTOR OR OP37 & RESISTOR 10 OP37 & RESISTOR (--) INPUT NOISE VOLTAGE - nV/ Hz 100 AD745 + RESISTOR ) ( An op amp's input voltage noise performance is typically divided into two regions: flatband and low frequency noise. The AD745 offers excellent performance with respect to both. The figure of 2.9 nV/ Hz @ 10 kHz is excellent for a JFET input amplifier. The 0.1 Hz to 10 Hz noise is typically 0.38 V p-p. The user should pay careful attention to several design details in order to optimize low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency noise: therefore sensitive circuitry should be well shielded from air flow. Keeping absolute chip temperature low also reduces low frequency noise in two ways: first, the low frequency noise is strongly dependent on the ambient temperature and increases above +25C. Secondly, since the gradient of temperature from the IC package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. Chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. Low frequency current noise can be computed from the ~ magnitude of the dc bias current I n = 2qI B f and increases below approximately 100 Hz with a 1/f power spectral density. For the AD745 the typical value of current noise is 6.9 fA/Hz at 1 kHz. Using the formula, ~ n = 4kT/R f , to compute the I Johnson noise of a resistor, expressed as a current, one can see that the current noise of the AD745 is equivalent to that of a 3.45 x 108 source resistance. At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the "real" part of the gate input impedance, which decreases with frequency. This noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude. RESISTOR NOISE ONLY (- - -) 1 100 1k 10k 100k 1M 10M SOURCE RESISTANCE - Figure 24. Total Input Noise Spectral Density @ 1 kHz vs. Source Resistance 100 In any FET input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. This noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pF in value. LOW NOISE CHARGE AMPLIFIERS INPUT OFFSET VOLTAGE - mV ADOP37G 10 1.0 As stated, the AD745 provides both low voltage and low current noise. This combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. When dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise. Charge (Q) is related to voltage and current by the simply stated fundamental relationships: dQ Q = CV and I = dt As shown, voltage, current and charge noise can all be directly related. The change in open circuit voltage (V) on a capacitor will equal the combination of the change in charge (Q/C) and the change in capacitance with a built-in charge (Q/C). AD745 KN 0.1 100 1k 10k 100k 1M 10M SOURCE RESISTANCE - Figure 25. Input Offset Voltage vs. Source Resistance REV. C -7- AD745 Figures 26 and 27 show two ways to buffer and amplify the output of a charge output transducer. Both require using an amplifier which has a very high input impedance, such as the AD745. Figure 26 shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the input of amplifier A1, which requires that the charge on capacitor CS be transferred to capacitor CF, thus yielding an output voltage of Q/CF. The amplifiers input voltage noise will appear at the output amplified by the noise gain (1 + (CS/CF)) of the circuit. CF Figure 28 shows that these two circuits have an identical frequency response and the same noise performance (provided that CS/CF = R1/ R2). One feature of the first circuit is that a "T" network is used to increase the effective resistance of RB and improve the low frequency cutoff point by the same factor. -100 -110 Hz DECIBELS REFERENCED TO 1V/ -120 -130 -140 -150 -160 -170 -180 -190 -200 -210 -220 0.01 0.1 1 10 100 1k 10k 100k NOISE DUE TO R B ALONE NOISE DUE TO I B ALONE FREQUENCY - Hz TOTAL OUTPUT NOISE RB R2 R1 CS A1 R1 R2 = CS CF C B* R B* Figure 28. Noise at the Outputs of the Circuits of Figures 26 and 27. Gain = 10, CS = 3000 pF, RB = 22 M Figure 26. A Charge Amplifier Circuit R1 C B* However, this does not change the noise contribution of RB which, in this example, dominates at low frequencies. The graph of Figure 29 shows how to select an RB large enough to minimize this resistor's contribution to overall circuit noise. When the equivalent current noise of RB (( 4 kT)/R) equals the noise of I B 2qI B , there is diminishing return in making RB larger. ( ) R2 R B* A2 5.2 x 10 10 CS *OPTIONAL, SEE TEXT RESISTANCE IN RB 5.2 x 10 9 Figure 27. Model for A High Z Follower with Gain 5.2 x 10 8 The second circuit, Figure 27, is simply a high impedance follower with gain. Here the noise gain (1 + (R1/R2)) is the same as the gain from the transducer to the output. Resistor RB, in both circuits, is required as a dc bias current return. There are three important sources of noise in these circuits. Amplifiers A1 and A2 contribute both voltage and current noise, while resistor RB contributes a current noise of: N 5.2 x 10 7 5.2 x 10 6 1pA 10pA 100pA 1nA INPUT BIAS CURRENT 10nA ~= T 4k f RB Figure 29. Graph of Resistance vs. Input Bias Current Where the Equivalent Noise 4 kT/R, Equals the Noise of the Bias Current I B 2qI B ( ) where: k = Boltzman's Constant = 1.381 x 10-23 Joules/Kelvin T = Absolute Temperature, Kelvin (0C = +273.2 Kelvin) f = Bandwidth - in Hz (Assuming an Ideal "Brick Wall" Filter) This must be root-sum-squared with the amplifier's own current noise. To maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. This is represented by the optional resistor RB in Figures 26 and 27. As previously mentioned, for best noise performance care should be taken to also balance the source capacitance designated by CB The value for CB in Figure 26 would be equal to CS in Figure 27. At values of CB over 300 pF, there is a diminishing impact on noise; capacitor CB can then be simply a large mylar bypass capacitor of 0.01 F or greater. -8- REV. C AD745 HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT INPUT BIAS CURRENT - pA 300 As with all JFET input amplifiers, the input bias current of the AD745 is a direct function of device junction temperature, IB approximately doubling every 10C. Figure 30 shows the relationship between bias current and junction temperature for the AD745. This graph shows that lowering the junction temperature will dramatically improve IB. 10 -6 TA = +25C 200 JA = 165C/W 100 JA = 115C/W 10 -7 INPUT BIAS CURRENT - Amps 10 -8 VS = +15V TA = +25C JA = 0C/W 0 5 10 SUPPLY VOLTAGE - Volts 15 10 -9 10 -10 Figure 32. Input Bias Current vs. Supply Voltage for Various Values of JA TJ 10 -11 10 -12 -60 -40 20 40 60 80 100 120 -20 0 JUNCTION TEMPERATURE - C 140 A (J TO DIE MOUNT) B (DIE MOUNT TO CASE) A + B = JC Figure 30. Input Bias Current vs. Junction Temperature The dc thermal properties of an IC can be closely approximated by using the simple model of Figure 31 where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance ( in C/watt). TJ JC CA TA CASE Figure 33. Breakdown of Various Package Thermal Resistance TA PIN JA REDUCED POWER SUPPLY OPERATION FOR LOWER IB WHERE: P IN TA TJ JC CA = DEVICE DISSIPATION = AMBIENT TEMPERATURE = JUNCTION TEMPERATURE = THERMAL RESISTANCE - JUNCTION TO CASE = THERMAL RESISTANCE - CASE TO AMBIENT Figure 31. Device Thermal Model Reduced power supply operation lowers IB in two ways: first, by lowering both the total power dissipation and, second, by reducing the basic gate-to-junction leakage (Figure 32). Figure 34 shows a 40 dB gain piezoelectric transducer amplifier, which operates without an ac coupling capacitor, over the -40C to +85C temperature range. If the optional coupling capacitor, C1, is used, this circuit will operate over the entire -55C to +125C temperature range. 100 C1* CT** +5V 10 8 ** TRANSDUCER CT 10 8 From this model TJ = TA+JA PIN. Therefore, IB can be determined in a particular application by using Figure 30 together with the published data for JA and power dissipation. The user can modify JA by use of an appropriate clip-on heat sink such as the Aavid #5801. JA is also a variable when using the AD745 in chip form. Figure 32 shows bias current vs. supply voltage with JA as the third variable. This graph can be used to predict bias current after JA has been computed. Again bias current will double for every 10C. The designer using the AD745 in chip form (Figure 33) must also be concerned with both JC and CA, since JC can be affected by the type of die mount technology used. Typically, JC's will be in the 3C to 5C/watt range; therefore, for normal packages, this small power dissipation level may be ignored. But, with a large hybrid substrate, JC will dominate proportionately more of the total JA. REV. C -9- 10k AD745 -5V *OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT Figure 34. A Piezoelectric Transducer AD745 TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS Two of the most popular charge-out transducers are hydrophones and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 35a and 35b show two ways in which to configure the AD745 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined by the value of capacitor C1 and is equal to: V OUT QOUT = C1 A dc servo loop (Figure 35b) can be used to assure a dc output <10 mV, without the need for a large compensating resistor when dealing with bias currents as large as 100 nA. For optimal low frequency performance, the time constant of the servo loop (R4C2 = R5C3) should be: R2 Time Constant 10 R1 1+ C1 R3 A LOW NOISE HYDROPHONE AMPLIFIER The ratio of capacitor C1 to the internal capacitance (CT) of the transducer determines the noise gain of this circuit (1 + CT/C1). The amplifiers voltage noise will appear at its output amplified by this amount. The low frequency bandwidth of these circuits will be dependent on the value of resistor R1. If a "T" network is used, the effective value is: R1 (1 + R2/R3). *pC = Picocoulombs g = Earth's Gravitational Constant C1 R1 110M (5x22M) R3 1k 1250pF R2 9k Hydrophones are usually calibrated in the voltage-out mode. The circuit of Figures 36a can be used to amplify the output of a typical hydrophone. If the optional ac coupling capacitor CC is used, the circuit will have a low frequency cutoff determined by an RC time constant equal to: Time Constant = 1 2 x CC x 100 where the dc gain is 1 and the gain above the low frequency cutoff (1/(2 CC(100 ))) is equal to (1 + R2/R3). The circuit of Figure 36b uses a dc servo loop to keep the dc output at 0 V and to maintain full dynamic range for IB's up to 100 nA. The time constant of R7 and C1 should be larger than that of R1 and CT for a smooth low frequency response. 1900 R3 100 R4* CC C1* R2 B&K MODEL 4370 OR EQUIVALENT AD745 OUTPUT 0.8mV/pC B&K TYPE 8100 HYDROPHONE CT AD745 OUTPUT 10 8 R1 INPUT SENSITIVITY = -179dB RE. 1V/Pa** *OPTIONAL, SEE TEXT ** 1 VOLT PER MICROPASCAL Figure 35a. A Basic Accelerometer Circuit C1 R1 110M (5x22M) R3 1250pF R2 9k 1k C2 2.2F 18M Figure 36a. A Low Noise Hydrophone Amplifier The transducer shown has a source capacitance of 7500 pF. For smaller transducer capacitances (300 pF), lowest noise can be achieved by adding a parallel RC network (R4 = R1, C1 = CT) in series with the inverting input of the AD745. 1900 R3 100 10 8 R4* R2 C1* OUTPUT 16M AD711 R4 R5 18M AD745 R4 0.27F C2 C3 2.2F B&K MODEL 4370 OR EQUIVALENT AD745 OUTPUT = 0.8mV/pC B&K TYPE 8100 HYDROPHONE R1 10 8 R5 AD711K 100k R6 1M CT *pC = PICOCOULOMBS g = EARTH'S GRAVITATIONAL CONSTANT 16M DC OUTPUT 1mV FOR IB (AD745) 100nA Figure 35b. An Accelerometer Circuit Employing a DC Servo Amplifier *OPTIONAL, SEE TEXT Figure 36b. A Hydrophone Amplifier Incorporating a DC Servo Loop -10- REV. C AD745 Design Considerations for I-to-V Converters 1F 0.01 F 1 -12V 2 0.01 F +12V 5 DIGITAL INPUTS 6 3k 7 8 -12V INPUT SOURCE: PHOTO DIODE, ACCELEROMETER, ECT. + There are some simple rules of thumb when designing an I-V converter where there is significant source capacitance (as with a photodiode) and bandwidth needs to be optimized. Consider the circuit of Figure 37. The high frequency noise gain (1 + CS/CL) is usually greater than five, so the AD745, with its higher slew rate and bandwidth is ideally suited to this application. Here both the low current and low voltage noise of the AD745 can be taken advantage of, since it is desirable in some instances to have a large RF (which increases sensitivity to input current noise) and, at the same time, operate the amplifier at high noise gain. RF +12V 16 AD1862 20 BIT D/A CONVERTER 15 14 13 12 0.01F +12V 0.1F OUTPUT 3 4 10F + ANALOG COMMON AD745 11 0.1F 10 TOP VIEW -12V 9 2000pF 100pF 3 POLE LOW PASS FILTER 0.01F CL DIGITAL COMMON IS RB CS AD745 Figure 38. A High Performance Audio DAC Circuit Figure 37. A Model for an l-to-V Converter In this circuit, the RF CS time constant limits the practical bandwidth over which flat response can be obtained, in fact: fB where: fB = signal bandwidth fC = gain bandwidth product of the amplifier With CL 1/(2 RF CS) the net response can be adjusted to a provide a two pole system with optimal flatness that has a corner frequency of fB. Capacitor CL adjusts the damping of the circuit's response. Note that bandwidth and sensitivity are directly traded off against each other via the selection of RF. For example, a photodiode with CS = 300 pF and RF = 100 k will have a maximum bandwidth of 360 kHz when capacitor CL 4.5 pF. Conversely, if only a 100 kHz bandwidth were required, then the maximum value of RF would be 360 k and that of capacitor CL still 4.5 pF. In either case, the AD745 provides impedance transformation, the effective transresistance, i.e., the I/V conversion gain, may be augmented with further gain. A wideband low noise amplifier such as the AD829 is recommended in this application. This principle can also be used to apply the AD745 in a high performance audio application. Figure 38 shows that an I-V converter of a high performance DAC, here the AD1862, can be designed to take advantage of the low voltage noise of the AD745 (2.9 nV/ Hz) as well as the high slew rate and bandwidth provided by decompensation. This circuit, with component values shown, has a 12 dB/octave rolloff at 728 kHz, with a passband ripple of less than 0.001 dB and a phase deviation of less than 2 degrees @ 20 kHz. fC 2 RF CS An important feature of this circuit is that high frequency energy, such as clock feedthrough, is shunted to common via a high quality capacitor and not the output stage of the amplifier, greatly reducing the error signal at the input of the amplifier and subsequent opportunities for intermodulation distortions. 40 RTI NOISE VOLTAGE nV/ Hz 30 UNBALANCED 20 10 BALANCED 2.9nV/ Hz 0 10 100 INPUT CAPACITANCE - pF 1000 Figure 39. RTI Noise Voltage vs. Input Capacitance BALANCING SOURCE IMPEDANCES As mentioned previously, it is good practice to balance the source impedances (both resistive and reactive) as seen by the inputs of the AD745. Balancing the resistive components will optimize dc performance over temperature because balancing will mitigate the effects of any bias current errors. Balancing input capacitance will minimize ac response errors due to the amplifier's input capacitance and, as shown in Figure 39, noise performance will be optimized. Figure 40 shows the required external components for noninverting (A) and inverting (B) configurations. REV. C -11- AD745 R1 CB = C F II C S RB = R1 II RS CF CB = C S RB = R S FOR R S >> R OR R 1 CB R1 2 RB OUTPUT OUTPUT R2 CS RS NONINVERTING CONNECTION RS CB RB INVERTING CONNECTION Figure 40. Optional External Components for Balancing Source Impedances OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic Mini-DIP (N) Package 8 0.31 (7.87) 1 4 5 0.25 (6.35) 0.39 (9.91) MAX 0.165 + 0.01 (4.19 + 0.25) SEATING PLANE 0.125 (3.18) MIN 0.18 + 0.03 (4.57 + 0.76) 0.035 + 0.01 (0.89 + 0.25) - 0.30 (7.62) REF 0.011 + 0.003 (0.28 + 0.08) - O.018 + 0.003 (0.46 + 0.08) - 0.100 (2.54) TYP 0 - 15 8-Pin Cerdip (Q) Package 0.005 (0.13) MIN 0.055 (1.35) MAX 16-Pin SOIC (R) Package 16 8 5 0.320 (8.13) 0.290 (7.37) 1 4 0.070 (1.78) 0.030 (0.76) 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.413 (10.49) 0.396 (10.11) 0.104 (2.64) 0.003 (2.36) 0.419 (10.64) 0.394 (10.01) 1 9 0.292 (7.42) 0.300 (7.62) 8 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) x 45 0.0098 (0.25) 0 -8 0.150 (3.81) MIN 0.100 (2.54) 0 - 15 BSC SEATING PLANE 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.060 (1.27) REF 0.019 (0.483) 0.014 (0.356) 0.0125 (0.32) 0.0091 (0.23) SEE DETAIL ABOVE 0.023 (0.58) 0.014 (0.36) -12- REV. C PRINTED IN U.S.A. 0.310 (7.87) 0.220 (5.59) 0.011 (0.279) 0.004 (0.102) C1507-24-2/91 AD745 CS AD745 |
Price & Availability of AD745JR-16
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